| BrunoLevy/learn-fpga |
2,225 |
|
0 |
0 |
about 2 years ago |
0 |
|
36 |
bsd-3-clause |
C++ |
| Learning FPGA, yosys, nextpnr, and RISC-V |
| Xilinx/Vitis-Tutorials |
972 |
|
0 |
0 |
about 2 years ago |
0 |
|
58 |
mit |
C |
| Vitis In-Depth Tutorials |
| hukenovs/dsp-theory |
792 |
|
0 |
0 |
about 3 years ago |
0 |
|
1 |
gpl-3.0 |
Jupyter Notebook |
| Theory of digital signal processing (DSP): signals, filtration (IIR, FIR, CIC, MAF), transforms (FFT, DFT, Hilbert, Z-transform) etc. |
| oneapi-src/oneAPI-samples |
758 |
|
0 |
0 |
about 2 years ago |
0 |
|
61 |
mit |
C++ |
| Samples for Intel® oneAPI Toolkits |
| lnis-uofu/OpenFPGA |
692 |
|
0 |
0 |
about 2 years ago |
0 |
|
103 |
mit |
Verilog |
| An Open-source FPGA IP Generator |
| fastmachinelearning/hls4ml-tutorial |
228 |
|
0 |
0 |
over 2 years ago |
0 |
|
18 |
|
Jupyter Notebook |
| Tutorial notebooks for hls4ml |
| Vitorian/awesome-fpga |
150 |
|
0 |
0 |
almost 9 years ago |
0 |
|
0 |
gpl-3.0 |
|
| A collection of resources on FPGA devices and development in general |
| intel/fpga-partial-reconfig |
84 |
|
0 |
0 |
about 2 years ago |
0 |
|
1 |
mit |
SystemVerilog |
| Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow |
| Xilinx/SDAccel-Tutorials |
75 |
|
0 |
0 |
about 6 years ago |
0 |
|
7 |
|
C++ |
| SDAccel Development Environment Tutorials |
| sy2002/QNICE-FPGA |
46 |
|
0 |
0 |
almost 5 years ago |
0 |
|
76 |
other |
Assembly |
| QNICE-FPGA is a 16-bit computer system for recreational programming built as a fully-fledged System-on-a-Chip in portable VHDL. |
