| VUnit/vunit |
651 |
|
1 |
5 |
over 2 years ago |
87 |
April 23, 2023 |
216 |
other |
VHDL |
| VUnit is a unit testing framework for VHDL/SystemVerilog |
| danielholanda/LeFlow |
329 |
|
0 |
0 |
over 6 years ago |
0 |
|
1 |
other |
Verilog |
| Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks |
| IObundle/iob-soc |
131 |
|
0 |
0 |
about 2 years ago |
0 |
|
8 |
mit |
Verilog |
| RISC-V System on Chip Template |
| TimRudy/ice-chips-verilog |
99 |
|
0 |
0 |
about 3 years ago |
0 |
|
4 |
gpl-3.0 |
Verilog |
| IceChips is a library of all common discrete logic devices in Verilog |
| ulx3s/fpga-odysseus |
58 |
|
0 |
0 |
over 2 years ago |
0 |
|
0 |
|
Verilog |
| FPGA Odysseus with ULX3S |
| MaxXSoft/Fuxi |
40 |
|
0 |
0 |
almost 5 years ago |
0 |
|
0 |
gpl-3.0 |
Verilog |
| Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3. |
| antmicro/usb-test-suite-build |
35 |
|
0 |
0 |
over 4 years ago |
0 |
|
4 |
apache-2.0 |
Shell |
| Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores |
| CTSRD-CHERI/bluecheck |
21 |
|
0 |
0 |
over 5 years ago |
0 |
|
0 |
other |
Bluespec |
| A generic test bench written in Bluespec |
| CMU-SAFARI/DRAM-Bender |
21 |
|
0 |
0 |
over 2 years ago |
0 |
|
1 |
mit |
VHDL |
| DRAM Bender is the first open source DRAM testing infrastructure that can be used to easily and comprehensively test state-of-the-art DDR4 modules of different form factors. Five prototypes are available on different FPGA boards. Described in our preprint: https://arxiv.org/pdf/2211.05838.pdf |
| tmeissner/libvhdl |
19 |
|
0 |
0 |
almost 4 years ago |
0 |
|
0 |
other |
VHDL |
| Library of reusable VHDL components |
