| mimblewimble/grin |
5,026 |
|
11 |
13 |
about 2 years ago |
28 |
March 17, 2022 |
133 |
apache-2.0 |
Rust |
| Minimal implementation of the Mimblewimble protocol. |
| google/skywater-pdk |
2,627 |
|
0 |
0 |
over 2 years ago |
1 |
July 24, 2022 |
192 |
apache-2.0 |
Python |
| Open source process design kit for usage with SkyWater Technology Foundry's 130nm node. |
| openhwgroup/cva6 |
1,946 |
|
0 |
0 |
about 2 years ago |
0 |
|
157 |
other |
Assembly |
| The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux |
| clash-lang/clash-compiler |
1,336 |
|
44 |
0 |
about 2 years ago |
87 |
November 11, 2023 |
280 |
other |
Haskell |
| Haskell to VHDL/Verilog/SystemVerilog compiler |
| olofk/serv |
1,158 |
|
0 |
0 |
over 2 years ago |
0 |
|
17 |
isc |
Verilog |
| SERV - The SErial RISC-V CPU |
| The-OpenROAD-Project/OpenLane |
1,091 |
|
0 |
0 |
over 2 years ago |
0 |
|
138 |
apache-2.0 |
Python |
| OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization. |
| olofk/fusesoc |
1,065 |
|
5 |
5 |
about 2 years ago |
26 |
November 17, 2023 |
119 |
bsd-2-clause |
Python |
| Package manager and build abstraction tool for FPGA/ASIC development |
| pulp-platform/axi |
834 |
|
0 |
0 |
over 2 years ago |
0 |
|
49 |
other |
SystemVerilog |
| AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication |
| riscvarchive/riscv-cores-list |
747 |
|
0 |
0 |
about 5 years ago |
0 |
|
|
|
|
| RISC-V Cores, SoC platforms and SoCs |
| esig/dss |
719 |
|
0 |
5 |
about 2 years ago |
6 |
November 03, 2023 |
3 |
lgpl-2.1 |
Java |
| Digital Signature Service : creation, extension and validation of advanced electronic signatures |
