| SpinalHDL/VexRiscv |
2,135 |
|
0 |
0 |
over 2 years ago |
0 |
|
100 |
mit |
Assembly |
| A FPGA friendly 32 bit RISC-V CPU implementation |
| openhwgroup/cva6 |
1,946 |
|
0 |
0 |
about 2 years ago |
0 |
|
157 |
other |
Assembly |
| The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux |
| darklife/darkriscv |
1,795 |
|
0 |
0 |
over 2 years ago |
0 |
|
9 |
bsd-3-clause |
Verilog |
| opensouce RISC-V cpu core implemented in Verilog from scratch in one night! |
| SI-RISCV/e200_opensource |
1,688 |
|
0 |
0 |
about 5 years ago |
0 |
|
33 |
apache-2.0 |
Verilog |
| Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2 |
| stnolting/neorv32 |
1,337 |
|
0 |
0 |
about 2 years ago |
0 |
|
15 |
bsd-3-clause |
VHDL |
| 🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. |
| olofk/serv |
1,158 |
|
0 |
0 |
over 2 years ago |
0 |
|
17 |
isc |
Verilog |
| SERV - The SErial RISC-V CPU |
| liangkangnan/tinyriscv |
865 |
|
0 |
0 |
over 2 years ago |
0 |
|
8 |
apache-2.0 |
C |
| A very simple and easy to understand RISC-V core. |
| firesim/firesim |
778 |
|
0 |
0 |
about 2 years ago |
0 |
|
218 |
other |
Scala |
| FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility |
| riscvarchive/riscv-cores-list |
747 |
|
0 |
0 |
about 5 years ago |
0 |
|
|
|
|
| RISC-V Cores, SoC platforms and SoCs |
| chipsalliance/Cores-VeeR-EH1 |
746 |
|
0 |
0 |
almost 3 years ago |
0 |
|
14 |
apache-2.0 |
SystemVerilog |
| VeeR EH1 core |
