| olofk/fusesoc |
1,428 |
|
5 |
5 |
15 days ago |
26 |
November 17, 2023 |
119 |
bsd-2-clause |
Python |
| Package manager and build abstraction tool for FPGA/ASIC development |
| verilog-to-routing/vtr-verilog-to-routing |
925 |
|
0 |
0 |
over 2 years ago |
0 |
|
447 |
other |
C++ |
| Verilog to Routing -- Open Source CAD Flow for FPGA Research |
| lnis-uofu/OpenFPGA |
692 |
|
0 |
0 |
over 2 years ago |
0 |
|
103 |
mit |
Verilog |
| An Open-source FPGA IP Generator |
| olofk/edalize |
573 |
|
2 |
3 |
over 2 years ago |
24 |
December 08, 2023 |
91 |
bsd-2-clause |
Python |
| An abstraction library for interfacing EDA tools |
| rggen/rggen |
261 |
|
0 |
0 |
over 2 years ago |
62 |
October 18, 2023 |
11 |
mit |
Ruby |
| Code generation tool for configuration and status registers |
| SystemRDL/systemrdl-compiler |
212 |
|
3 |
14 |
over 2 years ago |
50 |
November 09, 2023 |
8 |
mit |
Python |
| SystemRDL 2.0 language compiler front-end |
| Juniper/open-register-design-tool |
169 |
|
0 |
0 |
almost 3 years ago |
0 |
|
23 |
apache-2.0 |
Verilog |
| Tool to generate register RTL, models, and docs using SystemRDL or JSpec input |
| kactus2/kactus2dev |
168 |
|
0 |
0 |
over 2 years ago |
0 |
|
17 |
gpl-2.0 |
C++ |
| Kactus2 is a graphical EDA tool based on the IP-XACT standard. |
| TimRudy/ice-chips-verilog |
99 |
|
0 |
0 |
over 3 years ago |
0 |
|
4 |
gpl-3.0 |
Verilog |
| IceChips is a library of all common discrete logic devices in Verilog |
| chipsalliance/yosys-f4pga-plugins |
81 |
|
0 |
0 |
over 2 years ago |
0 |
|
83 |
apache-2.0 |
Verilog |
| Plugins for Yosys developed as part of the F4PGA project. |
