| verilog-to-routing/vtr-verilog-to-routing |
925 |
|
0 |
0 |
about 2 years ago |
0 |
|
447 |
other |
C++ |
| Verilog to Routing -- Open Source CAD Flow for FPGA Research |
| byuccl/spydrnet |
66 |
|
0 |
0 |
over 2 years ago |
21 |
September 14, 2023 |
44 |
bsd-3-clause |
Python |
| A flexible framework for analyzing and transforming FPGA netlists. Official repository. |
| rbkettlewell/trollstigen-fpga |
25 |
|
0 |
0 |
about 3 years ago |
0 |
|
2 |
|
PostScript |
| Open source fpga project leveraging vtr CAD flow. |
| JamesNewton/HybridDiskEncoder |
20 |
|
0 |
0 |
about 3 years ago |
0 |
|
1 |
|
C |
| Hybrid Disk Encoder: A lasercut Analog / Quadrature encoder with more than 1 MILLION CPR |
| byuccl/RapidSmith2 |
19 |
|
0 |
0 |
over 6 years ago |
0 |
|
46 |
other |
Java |
| RapidSmith2 - the Vivado successor to RapidSmith. Released Jan 4, 2017. |
| pkuzjx/eda-collection |
19 |
|
0 |
0 |
over 6 years ago |
0 |
|
0 |
|
|
| EliasVansteenkiste/FPGA-CAD-Framework |
14 |
|
0 |
0 |
over 6 years ago |
0 |
|
1 |
other |
Java |
| A Java framework focused on rapid prototyping of new CAD algorithms for FPGA compilation. |
| kim-sunghoon/Study-materials |
12 |
|
0 |
0 |
over 3 years ago |
0 |
|
0 |
mit |
|
| matthuszagh/fmcw |
5 |
|
0 |
0 |
over 5 years ago |
0 |
|
5 |
apache-2.0 |
Python |
| 6GHz frequency-modulated continuous-wave radar with real-time range detection |
