| logisim-evolution/logisim-evolution |
6,725 |
|
0 |
0 |
3 months ago |
0 |
|
209 |
gpl-3.0 |
Java |
| Digital logic design tool and simulator |
| hneemann/Digital |
3,476 |
|
0 |
0 |
about 2 years ago |
0 |
|
87 |
gpl-3.0 |
Java |
| A digital logic designer and circuit simulator. |
| SpinalHDL/VexRiscv |
2,135 |
|
0 |
0 |
over 2 years ago |
0 |
|
100 |
mit |
Assembly |
| A FPGA friendly 32 bit RISC-V CPU implementation |
| SpinalHDL/SpinalHDL |
1,912 |
|
0 |
4 |
3 months ago |
140 |
November 01, 2023 |
106 |
other |
Scala |
| Scala based HDL |
| cocotb/cocotb |
1,519 |
|
9 |
22 |
about 2 years ago |
44 |
October 06, 2023 |
415 |
bsd-3-clause |
Python |
| cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python |
| aws/aws-fpga |
1,366 |
|
0 |
0 |
almost 3 years ago |
0 |
|
15 |
other |
VHDL |
| Official repository of the AWS EC2 FPGA Hardware and Software Development Kit |
| stnolting/neorv32 |
1,337 |
|
0 |
0 |
about 2 years ago |
0 |
|
15 |
bsd-3-clause |
VHDL |
| 🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. |
| clash-lang/clash-compiler |
1,336 |
|
44 |
0 |
about 2 years ago |
87 |
November 11, 2023 |
280 |
other |
Haskell |
| Haskell to VHDL/Verilog/SystemVerilog compiler |
| olofk/fusesoc |
1,065 |
|
5 |
5 |
about 2 years ago |
26 |
November 17, 2023 |
119 |
bsd-2-clause |
Python |
| Package manager and build abstraction tool for FPGA/ASIC development |
| progranism/Open-Source-FPGA-Bitcoin-Miner |
902 |
|
0 |
0 |
over 12 years ago |
0 |
|
15 |
gpl-3.0 |
VHDL |
| A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the future of the Bitcoin project as a whole. A binary release is currently available for the Terasic DE2-115 Development Board, and there are compile-able projects for numerous boards. |
