| jpiat/hard-cv |
77 |
|
0 |
0 |
over 10 years ago |
0 |
|
0 |
|
VHDL |
| A repository of IPs for hardware computer vision (FPGA) |
| pgate1/SNES_on_FPGA |
68 |
|
0 |
0 |
over 2 years ago |
0 |
|
0 |
mit |
GLSL |
| implemented SNES on an FPGA. |
| dwesterg/soc-workshop |
14 |
|
0 |
0 |
almost 10 years ago |
0 |
|
1 |
|
C |
| pgate1/USB-Blaster_UART |
9 |
|
0 |
0 |
almost 3 years ago |
0 |
|
0 |
mit |
Verilog |
| UART via USB-Blaster with VirtualJTAG. |
| tommythorn/BeMicro-CV |
9 |
|
0 |
0 |
over 11 years ago |
0 |
|
1 |
|
VHDL |
| A "hello world" style designs for the Cyclone V based $49 Arrow BeMicro CV |
| uniabis/deocmpldcv |
8 |
|
0 |
0 |
almost 7 years ago |
0 |
|
0 |
|
VHDL |
| This project is a port of the 1chipMSX to DEOCM + DE0-CV including modification of OCM-PLD. |
| hukenovs/kapitanov.github.io |
5 |
|
0 |
0 |
over 3 years ago |
0 |
|
0 |
|
|
| CV. Kapitanov Alexander. Deep Learning Engineer, Ex. Lead FPGA developer. |
