| SpinalHDL/SpinalHDL |
1,912 |
|
0 |
4 |
3 months ago |
140 |
November 01, 2023 |
106 |
other |
Scala |
| Scala based HDL |
| darklife/darkriscv |
1,795 |
|
0 |
0 |
over 2 years ago |
0 |
|
9 |
bsd-3-clause |
Verilog |
| opensouce RISC-V cpu core implemented in Verilog from scratch in one night! |
| pulp-platform/axi |
834 |
|
0 |
0 |
over 2 years ago |
0 |
|
49 |
other |
SystemVerilog |
| AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication |
| firesim/firesim |
778 |
|
0 |
0 |
about 2 years ago |
0 |
|
218 |
other |
Scala |
| FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility |
| chipsalliance/Cores-VeeR-EH1 |
746 |
|
0 |
0 |
almost 3 years ago |
0 |
|
14 |
apache-2.0 |
SystemVerilog |
| VeeR EH1 core |
| open-sdr/openwifi-hw |
560 |
|
0 |
0 |
over 2 years ago |
0 |
|
5 |
agpl-3.0 |
Verilog |
| open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware |
| sergeykhbr/riscv_vhdl |
552 |
|
0 |
0 |
over 2 years ago |
0 |
|
2 |
apache-2.0 |
Verilog |
| Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators |
| trivialmips/nontrivial-mips |
362 |
|
0 |
0 |
almost 6 years ago |
0 |
|
0 |
other |
SystemVerilog |
| NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux. |
| facebookresearch/deepfloat |
333 |
|
0 |
0 |
over 7 years ago |
0 |
|
3 |
other |
SystemVerilog |
| An exploration of log domain "alternative floating point" for hardware ML/AI accelerators. |
| chipsalliance/Cores-VeeR-EL2 |
323 |
|
0 |
0 |
about 1 month ago |
0 |
|
33 |
apache-2.0 |
SystemVerilog |
| VeeR EL2 Core |
