| riscv/riscv-v-spec |
801 |
|
0 |
0 |
over 2 years ago |
0 |
|
125 |
cc-by-4.0 |
Assembly |
| Working draft of the proposed RISC-V V vector extension |
| pulp-platform/ara |
276 |
|
0 |
0 |
over 2 years ago |
0 |
|
57 |
other |
C |
| The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core |
| riscv-ovpsim/imperas-riscv-tests |
123 |
|
0 |
0 |
over 2 years ago |
0 |
|
12 |
|
C |
| JishinMaster/simd_utils |
65 |
|
0 |
0 |
over 2 years ago |
0 |
|
2 |
bsd-2-clause |
C |
| A header only library implementing common mathematical functions using SIMD intrinsics |
| RALC88/riscv-vectorized-benchmark-suite |
48 |
|
0 |
0 |
over 3 years ago |
0 |
|
3 |
other |
C++ |
| RiVEC Bencmark Suite |
| SingularityKChen/dl_accelerator |
44 |
|
0 |
0 |
almost 6 years ago |
0 |
|
5 |
|
Scala |
| Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions |
| jiegec/rvv-kernels |
16 |
|
0 |
0 |
about 3 years ago |
0 |
|
0 |
|
Assembly |
| Implements kernels with RISC-V Vector |
| compiler-dev/llvm-rv |
11 |
|
0 |
0 |
over 5 years ago |
0 |
|
2 |
|
C++ |
| Full Support 32bit RISC-V in LLVM and CLANG for Vector Extension |
| jasonlin316/RISC-V-CPU |
6 |
|
0 |
0 |
over 6 years ago |
0 |
|
1 |
|
Verilog |
| A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology. |
| gsauthof/riscv |
5 |
|
0 |
0 |
over 5 years ago |
0 |
|
0 |
|
Assembly |
| RISC-V vector and other assembly code examples |
