| darklife/darkriscv |
1,795 |
|
0 |
0 |
over 2 years ago |
0 |
|
9 |
bsd-3-clause |
Verilog |
| opensouce RISC-V cpu core implemented in Verilog from scratch in one night! |
| JulianKemmerer/PipelineC |
519 |
|
0 |
0 |
about 2 years ago |
0 |
|
82 |
gpl-3.0 |
Python |
| A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature. |
| leros-dev/leros |
87 |
|
0 |
0 |
over 2 years ago |
0 |
|
3 |
bsd-2-clause |
VHDL |
| A Tiny Processor Core |
| p4fpga/p4fpga |
46 |
|
0 |
0 |
over 8 years ago |
0 |
|
11 |
bsd-2-clause |
Bluespec |
| P4-14/16 Bluespec Compiler |
| pedrorivera/SiaFpgaMiner |
44 |
|
0 |
0 |
about 8 years ago |
0 |
|
1 |
mit |
VHDL |
| VHDL FPGA design of an optimized Blake2b pipeline to mine Siacoin |
| Evensgn/RISC-V-CPU |
34 |
|
0 |
0 |
over 8 years ago |
0 |
|
1 |
|
Verilog |
| RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL. |
| panda5mt/KyogenRV |
25 |
|
0 |
0 |
about 5 years ago |
0 |
|
0 |
apache-2.0 |
Scala |
| The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA. |
| FedericoSerafini/HLS-CNN |
19 |
|
0 |
0 |
over 2 years ago |
0 |
|
0 |
mit |
C |
| High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition. |
| osmhpi/metalfs |
14 |
|
0 |
0 |
about 4 years ago |
0 |
|
3 |
mit |
C++ |
| Near-storage compute aware file system and FPGA operator pipelines. |
| jherkenhoff/Bitmap-VHDL-Package |
9 |
|
0 |
0 |
over 8 years ago |
0 |
|
|
mit |
VHDL |
| A vhdl package for reading and writing bitmap files. |
