| open-sdr/openwifi |
3,363 |
|
0 |
0 |
over 2 years ago |
0 |
|
51 |
agpl-3.0 |
C |
| open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software |
| fastmachinelearning/hls4ml |
1,913 |
|
0 |
0 |
21 days ago |
10 |
November 16, 2023 |
164 |
apache-2.0 |
Python |
| Machine learning on FPGAs using HLS |
| pConst/basic_verilog |
1,333 |
|
0 |
0 |
over 2 years ago |
0 |
|
0 |
|
Verilog |
| Must-have verilog systemverilog modules |
| doonny/PipeCNN |
916 |
|
0 |
0 |
about 4 years ago |
0 |
|
35 |
apache-2.0 |
C |
| An OpenCL-based FPGA Accelerator for Convolutional Neural Networks |
| m-labs/nmigen |
589 |
|
0 |
0 |
over 4 years ago |
0 |
|
39 |
other |
Python |
| A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen |
| open-sdr/openwifi-hw |
560 |
|
0 |
0 |
over 2 years ago |
0 |
|
5 |
agpl-3.0 |
Verilog |
| open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware |
| fpgasystems/fpga-network-stack |
559 |
|
0 |
0 |
over 2 years ago |
0 |
|
17 |
bsd-3-clause |
C++ |
| Scalable Network Stack for FPGAs (TCP/IP, RoCEv2) |
| JulianKemmerer/PipelineC |
519 |
|
0 |
0 |
about 2 years ago |
0 |
|
82 |
gpl-3.0 |
Python |
| A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature. |
| dgschwend/zynqnet |
510 |
|
0 |
0 |
almost 9 years ago |
0 |
|
38 |
gpl-3.0 |
HTML |
| Master Thesis "ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural Network" |
| xupsh/pp4fpgas-cn |
394 |
|
0 |
0 |
over 4 years ago |
0 |
|
7 |
|
CSS |
| 中文版 Parallel Programming for FPGAs |
