| fitzgen/synth-loop-free-prog |
37 |
|
0 |
0 |
about 6 years ago |
0 |
|
0 |
|
Rust |
| Synthesis of Loop-free Programs in Rust |
| SaswatPadhi/LoopInvGen |
31 |
|
0 |
0 |
almost 6 years ago |
0 |
|
2 |
mit |
OCaml |
| Generates loop invariants for program verification |
| meelgroup/manthan |
26 |
|
0 |
0 |
over 2 years ago |
0 |
|
1 |
other |
Python |
| Manthan for Boolean function synthesis |
| jinwookjungs/datc_robust_design_flow |
15 |
|
0 |
0 |
about 6 years ago |
0 |
|
2 |
gpl-3.0 |
Verilog |
| DATC Robust Design Flow. |
| ieee-ceda-datc/RDF-2019 |
14 |
|
0 |
0 |
over 5 years ago |
0 |
|
0 |
mit |
Verilog |
| DATC RDF |
| thelmuth/program-synthesis-benchmark-datasets |
9 |
|
0 |
0 |
over 3 years ago |
0 |
|
1 |
mit |
Shell |
| Repository of datasets for the General Program Synthesis Benchmark Suite |
| masc-ucsc/anubis |
8 |
|
0 |
0 |
over 7 years ago |
0 |
|
0 |
other |
C |
| The ANUBIS benchmark suite for Incremental Synthesis |
| umangm/realsyn |
7 |
|
0 |
0 |
almost 8 years ago |
0 |
|
0 |
|
Python |
| Automated Controller Synthesis |
| jinwookjungs/open_design_flow |
7 |
|
0 |
0 |
over 7 years ago |
0 |
|
1 |
|
Python |
| OpenDesign Flow Database |
| jfrankle/refinements-popl-16 |
7 |
|
0 |
0 |
over 10 years ago |
0 |
|
0 |
|
F# |
| Artifact of "Example-Directed Synthesis: A Type-Theoretic Implementation" by Frankle, Osera, Walker, and Zdancewic. |
