| cariboulabs/cariboulite |
1,005 |
|
0 |
0 |
about 2 years ago |
0 |
|
73 |
|
C |
| CaribouLite turns any 40-pin Raspberry-Pi into a Tx/Rx 6GHz SDR |
| EttusResearch/uhd |
869 |
|
0 |
3 |
over 2 years ago |
11 |
September 14, 2022 |
93 |
other |
Verilog |
| The USRP™ Hardware Driver Repository |
| Nuand/bladeRF-wiphy |
255 |
|
0 |
0 |
about 4 years ago |
0 |
|
4 |
gpl-2.0 |
VHDL |
| bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem |
| maia-sdr/maia-sdr |
144 |
|
1 |
2 |
over 2 years ago |
7 |
April 12, 2025 |
1 |
|
Python |
| Maia SDR is an open-source FPGA-based SDR project focusing on the ADALM Pluto |
| ucsdsysnet/sparsdr |
54 |
|
0 |
0 |
about 3 years ago |
0 |
|
18 |
|
Python |
| oscimp/oscimpDigital |
46 |
|
0 |
0 |
over 2 years ago |
0 |
|
1 |
other |
|
| OscillatorIMP ecosystem for the digital characterization of ultrastable oscillators and Software Defined Radio (SDR) frontend processing |
| greatscottgadgets/amalthea |
32 |
|
0 |
0 |
about 3 years ago |
0 |
|
1 |
bsd-3-clause |
Python |
| an experimental SDR platform |
| greatfet-hardware/quince |
24 |
|
0 |
0 |
over 4 years ago |
0 |
|
1 |
bsd-3-clause |
|
| a 2.4 GHz SDR neighbor using 1 bit ADC |
| ucsdsysnet/SweepSense |
23 |
|
0 |
0 |
over 2 years ago |
0 |
|
2 |
apache-2.0 |
Python |
| FPGA code and Python API for adding chirp functionality to USRP N210 with CBX daughter board, after the required hardware modification. |
| Gordonei/MyHDL-based-FPGA-DSP-Toolflow |
21 |
|
0 |
0 |
over 13 years ago |
0 |
|
0 |
|
Python |
| A library for generating Software Defined Radio-intended DSP code for FPGAs that makes use of the MyHDL (www.myhdl.org) Python library. Targeted at the Rhino Project (see URL). |
