| openhwgroup/cva6 |
1,946 |
|
0 |
0 |
about 2 years ago |
0 |
|
157 |
other |
Assembly |
| The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux |
| clash-lang/clash-compiler |
1,336 |
|
44 |
0 |
about 2 years ago |
87 |
November 11, 2023 |
280 |
other |
Haskell |
| Haskell to VHDL/Verilog/SystemVerilog compiler |
| olofk/serv |
1,158 |
|
0 |
0 |
over 2 years ago |
0 |
|
17 |
isc |
Verilog |
| SERV - The SErial RISC-V CPU |
| olofk/fusesoc |
1,065 |
|
5 |
5 |
about 2 years ago |
26 |
November 17, 2023 |
119 |
bsd-2-clause |
Python |
| Package manager and build abstraction tool for FPGA/ASIC development |
| pulp-platform/axi |
834 |
|
0 |
0 |
over 2 years ago |
0 |
|
49 |
other |
SystemVerilog |
| AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication |
| riscvarchive/riscv-cores-list |
747 |
|
0 |
0 |
about 5 years ago |
0 |
|
|
|
|
| RISC-V Cores, SoC platforms and SoCs |
| VUnit/vunit |
651 |
|
1 |
5 |
over 2 years ago |
87 |
April 23, 2023 |
216 |
other |
VHDL |
| VUnit is a unit testing framework for VHDL/SystemVerilog |
| zssloth/Embedded-Neural-Network |
547 |
|
0 |
0 |
about 7 years ago |
0 |
|
|
|
|
| collection of works aiming at reducing model sizes or the ASIC/FPGA accelerator for machine learning |
| ultraembedded/riscv |
364 |
|
0 |
0 |
over 4 years ago |
0 |
|
4 |
bsd-3-clause |
Verilog |
| RISC-V CPU Core (RV32IM) |
| VLSI-EDA/PoC |
324 |
|
0 |
0 |
over 5 years ago |
0 |
|
31 |
other |
VHDL |
| IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany |
