| Tencent/ncnn |
18,693 |
|
0 |
1 |
about 2 years ago |
26 |
October 27, 2023 |
1,010 |
other |
C++ |
| ncnn is a high-performance neural network inference framework optimized for the mobile platform |
| unicorn-engine/unicorn |
6,921 |
|
0 |
4 |
about 2 years ago |
8 |
November 01, 2022 |
87 |
gpl-2.0 |
C |
| Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86) |
| SpinalHDL/VexRiscv |
2,135 |
|
0 |
0 |
over 2 years ago |
0 |
|
100 |
mit |
Assembly |
| A FPGA friendly 32 bit RISC-V CPU implementation |
| openhwgroup/cva6 |
1,946 |
|
0 |
0 |
about 2 years ago |
0 |
|
157 |
other |
Assembly |
| The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux |
| darklife/darkriscv |
1,795 |
|
0 |
0 |
over 2 years ago |
0 |
|
9 |
bsd-3-clause |
Verilog |
| opensouce RISC-V cpu core implemented in Verilog from scratch in one night! |
| larsbrinkhoff/awesome-cpus |
1,735 |
|
0 |
0 |
over 3 years ago |
0 |
|
1 |
cc0-1.0 |
HTML |
| All CPU and MCU documentation in one place |
| SI-RISCV/e200_opensource |
1,688 |
|
0 |
0 |
about 5 years ago |
0 |
|
33 |
apache-2.0 |
Verilog |
| Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2 |
| stnolting/neorv32 |
1,337 |
|
0 |
0 |
about 2 years ago |
0 |
|
15 |
bsd-3-clause |
VHDL |
| 🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. |
| openhwgroup/cv32e40p |
836 |
|
0 |
0 |
about 2 years ago |
0 |
|
52 |
other |
SystemVerilog |
| CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform |
| riscv-mcu/e203_hbirdv2 |
741 |
|
0 |
0 |
about 3 years ago |
0 |
|
10 |
apache-2.0 |
Verilog |
| The Ultra-Low Power RISC-V Core |
