| darklife/darkriscv |
1,795 |
|
0 |
0 |
over 2 years ago |
0 |
|
9 |
bsd-3-clause |
Verilog |
| opensouce RISC-V cpu core implemented in Verilog from scratch in one night! |
| openhwgroup/cv32e40p |
836 |
|
0 |
0 |
about 2 years ago |
0 |
|
52 |
other |
SystemVerilog |
| CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform |
| sergeykhbr/riscv_vhdl |
552 |
|
0 |
0 |
over 2 years ago |
0 |
|
2 |
apache-2.0 |
Verilog |
| Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators |
| Fadezed/concurrency |
537 |
|
0 |
0 |
over 3 years ago |
0 |
|
2 |
|
Java |
| Java 并发编程知识梳理以及常见处理模式 features and patterns |
| trivialmips/nontrivial-mips |
362 |
|
0 |
0 |
almost 6 years ago |
0 |
|
0 |
other |
SystemVerilog |
| NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux. |
| WangXuan95/USTC-RVSoC |
261 |
|
0 |
0 |
over 2 years ago |
0 |
|
4 |
gpl-3.0 |
SystemVerilog |
| An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。 |
| KASIRGA-KIZIL/tekno-kizil |
129 |
|
0 |
0 |
over 2 years ago |
0 |
|
3 |
gpl-3.0 |
Verilog |
| KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi |
| bluespec/Toooba |
126 |
|
0 |
0 |
over 2 years ago |
0 |
|
3 |
other |
Verilog |
| RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT |
| jamieiles/oldland-cpu |
89 |
|
0 |
0 |
about 10 years ago |
0 |
|
1 |
|
Verilog |
| Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools |
| mzpqnxow/realtek-mips-sdks |
50 |
|
0 |
0 |
about 3 years ago |
0 |
|
0 |
|
C |
| Realtek Network SoC/CPU toolchains (including support for Lexra based chips) |
