| pervognsen/bitwise |
4,582 |
|
0 |
0 |
about 7 years ago |
0 |
|
17 |
other |
C |
| Bitwise is an educational project where we create the software/hardware stack for a computer from scratch. |
| definelicht/hlslib |
236 |
|
0 |
0 |
about 3 years ago |
0 |
|
5 |
bsd-3-clause |
C++ |
| A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life. |
| cliffordwolf/SimpleVOut |
112 |
|
0 |
0 |
over 7 years ago |
0 |
|
0 |
|
Verilog |
| A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals |
| antmicro/fastvdma |
92 |
|
0 |
0 |
over 2 years ago |
0 |
|
5 |
apache-2.0 |
Scala |
| Antmicro's fast, vendor-neutral DMA IP in Chisel |
| mmicko/prjtang |
79 |
|
0 |
0 |
over 3 years ago |
0 |
|
0 |
isc |
C++ |
| Documenting the Anlogic FPGA bit-stream format. |
| WangXuan95/Verilog-UART |
56 |
|
0 |
0 |
over 2 years ago |
0 |
|
0 |
gpl-3.0 |
Verilog |
| 3 modules: UART receiver, UART transmitter, UART to AXI4 master. 3个模块：UART接收器、UART发送器、UART转AXI4交互式调试器 |
| myriadrf/STREAM |
24 |
|
0 |
0 |
over 10 years ago |
0 |
|
0 |
|
VHDL |
| FPGA development platform for high-performance RF and digital design |
| suoto/fpga_cores |
21 |
|
0 |
0 |
almost 3 years ago |
0 |
|
0 |
other |
VHDL |
| FedericoSerafini/HLS-CNN |
19 |
|
0 |
0 |
over 2 years ago |
0 |
|
0 |
mit |
C |
| High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition. |
| samawati/j1eforth |
14 |
|
0 |
0 |
about 11 years ago |
0 |
|
1 |
|
Forth |
| eForth for the j1 simulator and actual J1 FPGAs |
