| cliffordwolf/SimpleVOut |
112 |
|
0 |
0 |
over 7 years ago |
0 |
|
0 |
|
Verilog |
| A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals |
| WangXuan95/Verilog-UART |
56 |
|
0 |
0 |
over 2 years ago |
0 |
|
0 |
gpl-3.0 |
Verilog |
| 3 modules: UART receiver, UART transmitter, UART to AXI4 master. 3个模块：UART接收器、UART发送器、UART转AXI4交互式调试器 |
| sergicuen/collection-iPxs |
33 |
|
0 |
0 |
almost 8 years ago |
0 |
|
0 |
gpl-2.0 |
Verilog |
| Icestudio Pixel Stream collection |
| wavedrom/vcd |
32 |
|
0 |
3 |
about 2 years ago |
27 |
March 12, 2023 |
16 |
mit |
JavaScript |
| Value Change Dump (VCD) parser |
| benreynwar/fpga-sdrlib |
13 |
|
0 |
0 |
over 13 years ago |
0 |
|
0 |
mit |
Python |
| Verilog modules for software-defined radio. |
| mattzgto/bladerf-dvbs2 |
9 |
|
0 |
0 |
about 8 years ago |
0 |
|
0 |
|
Verilog |
| 16-APSK DVB-S2 Transmitter for BladeRF |
| lucasbrasilino/net2axis |
9 |
|
0 |
0 |
over 6 years ago |
0 |
|
0 |
isc |
Verilog |
| Verilog network module. Models network traffic from pcap to AXI-Stream |
| alexforencich/verilog-ft245 |
8 |
|
0 |
0 |
almost 8 years ago |
0 |
|
0 |
mit |
Python |
| Verilog FT245 to AXI stream interface |
| catkira/complex_multiplier |
8 |
|
0 |
0 |
about 3 years ago |
0 |
|
0 |
|
Python |
| HDL code for a complex multiplier with AXI stream Interface |
| jhol/otl-icoboard-pmodoledrgb-demo |
6 |
|
0 |
0 |
over 8 years ago |
0 |
|
0 |
bsd-3-clause |
Verilog |
| A demo project that uses the IcoBoard to render graphics on a PmodOLEDrgb display |
