| chipsalliance/chisel |
3,593 |
|
0 |
9 |
about 2 years ago |
59 |
April 14, 2023 |
397 |
apache-2.0 |
Scala |
| Chisel: A Modern Hardware Design Language |
| verilator/verilator |
1,934 |
|
0 |
1 |
about 2 years ago |
8 |
October 04, 2022 |
304 |
lgpl-3.0 |
C++ |
| Verilator open-source SystemVerilog simulator and lint system |
| SpinalHDL/SpinalHDL |
1,912 |
|
0 |
4 |
3 months ago |
140 |
November 01, 2023 |
106 |
other |
Scala |
| Scala based HDL |
| darklife/darkriscv |
1,795 |
|
0 |
0 |
over 2 years ago |
0 |
|
9 |
bsd-3-clause |
Verilog |
| opensouce RISC-V cpu core implemented in Verilog from scratch in one night! |
| nvdla/hw |
1,254 |
|
0 |
0 |
about 4 years ago |
0 |
|
193 |
other |
Verilog |
| RTL, Cmodel, and testbench for NVDLA |
| The-OpenROAD-Project/OpenROAD |
1,102 |
|
0 |
0 |
about 2 years ago |
0 |
|
282 |
bsd-3-clause |
Verilog |
| OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/ |
| The-OpenROAD-Project/OpenLane |
1,091 |
|
0 |
0 |
over 2 years ago |
0 |
|
138 |
apache-2.0 |
Python |
| OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization. |
| syntacore/scr1 |
688 |
|
0 |
0 |
over 2 years ago |
0 |
|
3 |
other |
SystemVerilog |
| SCR1 is a high-quality open-source RISC-V MCU core in Verilog |
| open-sdr/openwifi-hw |
560 |
|
0 |
0 |
over 2 years ago |
0 |
|
5 |
agpl-3.0 |
Verilog |
| open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware |
| sergeykhbr/riscv_vhdl |
552 |
|
0 |
0 |
over 2 years ago |
0 |
|
2 |
apache-2.0 |
Verilog |
| Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators |
