| logisim-evolution/logisim-evolution |
6,725 |
|
0 |
0 |
3 months ago |
0 |
|
209 |
gpl-3.0 |
Java |
| Digital logic design tool and simulator |
| chipsalliance/chisel |
3,593 |
|
0 |
9 |
about 2 years ago |
59 |
April 14, 2023 |
397 |
apache-2.0 |
Scala |
| Chisel: A Modern Hardware Design Language |
| hneemann/Digital |
3,476 |
|
0 |
0 |
about 2 years ago |
0 |
|
87 |
gpl-3.0 |
Java |
| A digital logic designer and circuit simulator. |
| open-sdr/openwifi |
3,363 |
|
0 |
0 |
over 2 years ago |
0 |
|
51 |
agpl-3.0 |
C |
| open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software |
| YosysHQ/yosys |
2,998 |
|
0 |
0 |
about 2 years ago |
0 |
|
435 |
isc |
C++ |
| Yosys Open SYnthesis Suite |
| steveicarus/iverilog |
2,521 |
|
0 |
0 |
about 2 years ago |
0 |
|
125 |
gpl-2.0 |
C++ |
| Icarus Verilog |
| SpinalHDL/VexRiscv |
2,135 |
|
0 |
0 |
over 2 years ago |
0 |
|
100 |
mit |
Assembly |
| A FPGA friendly 32 bit RISC-V CPU implementation |
| verilator/verilator |
1,934 |
|
0 |
1 |
about 2 years ago |
8 |
October 04, 2022 |
304 |
lgpl-3.0 |
C++ |
| Verilator open-source SystemVerilog simulator and lint system |
| SpinalHDL/SpinalHDL |
1,912 |
|
0 |
4 |
3 months ago |
140 |
November 01, 2023 |
106 |
other |
Scala |
| Scala based HDL |
| jbush001/NyuziProcessor |
1,863 |
|
0 |
0 |
about 2 years ago |
0 |
|
90 |
apache-2.0 |
C |
| GPGPU microprocessor architecture |
