| alexforencich/verilog-ethernet |
1,768 |
|
0 |
0 |
about 2 years ago |
0 |
|
98 |
mit |
Verilog |
| Verilog Ethernet components for FPGA implementation |
| WangXuan95/FPGA-RMII-SMII |
51 |
|
0 |
0 |
over 2 years ago |
0 |
|
0 |
gpl-3.0 |
Verilog |
| An FPGA-based MII to RMII & SMII converter to connect 100M ethernet PHY chip such as LAN8720 or KSZ8041TLI-S. 基于FPGA的MII转RMII和MII转SMII，用来连接LAN8720、KSZ8041TLI-S等百兆以太网PHY芯片。 |
| tmatsuya/wiki |
31 |
|
0 |
0 |
about 9 years ago |
0 |
|
0 |
|
Verilog |
| andres-mancera/ethernet_10ge_mac_SV_UVM_tb |
30 |
|
0 |
0 |
over 7 years ago |
0 |
|
0 |
|
Verilog |
| SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core |
| cjhonlyone/picorv32_Xilinx |
19 |
|
0 |
0 |
almost 6 years ago |
0 |
|
0 |
mit |
Verilog |
| A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz |
| freecores/ethmac |
19 |
|
0 |
0 |
over 6 years ago |
0 |
|
0 |
|
Verilog |
| Ethernet MAC 10/100 Mbps |
| forconesi/nfmac10g |
17 |
|
0 |
0 |
about 9 years ago |
0 |
|
0 |
|
Verilog |
| Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC |
| andres-mancera/ethernet_10ge_mac_SV_tb |
16 |
|
0 |
0 |
about 10 years ago |
0 |
|
0 |
|
Verilog |
| SystemVerilog testbench for an Ethernet 10GE MAC core |
| sora/ethpipe |
14 |
|
0 |
0 |
over 11 years ago |
0 |
|
1 |
|
Verilog |
| EtherPIPE: an Ethernet character device for packet processing |
| KoroB14/DVP_to_UDP |
11 |
|
0 |
0 |
about 5 years ago |
0 |
|
0 |
gpl-3.0 |
Verilog |
| Uncompressed video uver UDP using 1000BASE-T Ethernet on Cyclone IV FPGA |
