| EttusResearch/uhd |
869 |
|
0 |
3 |
over 2 years ago |
11 |
September 14, 2022 |
93 |
other |
Verilog |
| The USRP™ Hardware Driver Repository |
| ZipCPU/sdr |
56 |
|
0 |
0 |
about 2 years ago |
0 |
|
0 |
|
Verilog |
| A basic Soft(Gate)ware Defined Radio architecture |
| B0WEN-HU/gr-verilog |
29 |
|
0 |
0 |
over 6 years ago |
0 |
|
1 |
gpl-3.0 |
C++ |
| This is an OOT module for GNU Radio integrating verilog simulation feature |
| tmolteno/TART |
20 |
|
2 |
3 |
almost 4 years ago |
25 |
December 02, 2023 |
34 |
lgpl-3.0 |
Verilog |
| Transient Array Radio Telescope |
| benreynwar/fpga-sdrlib |
13 |
|
0 |
0 |
over 13 years ago |
0 |
|
0 |
mit |
Python |
| Verilog modules for software-defined radio. |
| andykarpov/radio-86rk-wxeda |
12 |
|
0 |
0 |
about 11 years ago |
0 |
|
0 |
bsd-2-clause |
Verilog |
| Port of the original radio-86rk_SDRAM Altera DE1 code to the WXEDA board |
| marsohod4you/Fpga-PM-Radio |
9 |
|
0 |
0 |
almost 9 years ago |
0 |
|
0 |
|
Verilog |
| Implement Phase Modulation Radio Transmitter in FPGA Altera MAX10, with Marsohod3bis FPGA board. |
| mesarcik/DRFM |
5 |
|
0 |
0 |
over 4 years ago |
0 |
|
0 |
|
Verilog |
| Code for paper entitled "Low Cost FPGA based Implementation of a DRFM System" |
| pengyuzhang/FreeRider |
5 |
|
0 |
0 |
over 8 years ago |
0 |
|
0 |
|
Verilog |
