| cocotb/cocotb |
1,519 |
|
9 |
22 |
about 2 years ago |
44 |
October 06, 2023 |
415 |
bsd-3-clause |
Python |
| cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python |
| syntacore/scr1 |
688 |
|
0 |
0 |
over 2 years ago |
0 |
|
3 |
other |
SystemVerilog |
| SCR1 is a high-quality open-source RISC-V MCU core in Verilog |
| zachjs/sv2v |
429 |
|
0 |
0 |
about 2 years ago |
4 |
June 22, 2023 |
22 |
bsd-3-clause |
Haskell |
| SystemVerilog to Verilog conversion |
| danielholanda/LeFlow |
329 |
|
0 |
0 |
over 6 years ago |
0 |
|
1 |
other |
Verilog |
| Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks |
| NNgen/nngen |
281 |
|
0 |
0 |
over 2 years ago |
5 |
September 12, 2023 |
31 |
apache-2.0 |
Python |
| NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network |
| PyHDI/veriloggen |
275 |
|
1 |
0 |
over 2 years ago |
75 |
September 12, 2023 |
19 |
apache-2.0 |
Python |
| Veriloggen: A Mixed-Paradigm Hardware Construction Framework |
| dawsonjon/fpu |
257 |
|
0 |
0 |
over 4 years ago |
0 |
|
13 |
mit |
Verilog |
| synthesiseable ieee 754 floating point library in verilog |
| veripool/verilog-mode |
231 |
|
0 |
0 |
about 2 years ago |
0 |
|
46 |
gpl-3.0 |
SystemVerilog |
| Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org. |
| riscv/riscv-bitmanip |
174 |
|
0 |
0 |
over 3 years ago |
0 |
|
44 |
cc-by-4.0 |
Makefile |
| Working draft of the proposed RISC-V Bitmanipulation extension |
| IObundle/iob-soc |
131 |
|
0 |
0 |
about 2 years ago |
0 |
|
8 |
mit |
Verilog |
| RISC-V System on Chip Template |
