| doonny/PipeCNN |
916 |
|
0 |
0 |
about 4 years ago |
0 |
|
35 |
apache-2.0 |
C |
| An OpenCL-based FPGA Accelerator for Convolutional Neural Networks |
| dgschwend/zynqnet |
510 |
|
0 |
0 |
almost 9 years ago |
0 |
|
38 |
gpl-3.0 |
HTML |
| Master Thesis "ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural Network" |
| sld-columbia/esp |
267 |
|
0 |
0 |
over 2 years ago |
0 |
|
34 |
other |
C |
| Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy |
| changwoolee/lenet5_hls |
188 |
|
0 |
0 |
over 4 years ago |
0 |
|
12 |
mit |
C++ |
| FPGA Accelerator for CNN using Vivado HLS |
| Xtra-Computing/ThunderGP |
90 |
|
0 |
0 |
over 3 years ago |
0 |
|
2 |
apache-2.0 |
C++ |
| HLS-based Graph Processing Framework on FPGAs |
| jiangwx/SkrSkr |
76 |
|
0 |
0 |
almost 4 years ago |
0 |
|
4 |
other |
Tcl |
| The second place winner for DAC-SDC 2020 |
| pp-Innovate/FPGA-ZynqNet |
56 |
|
0 |
0 |
almost 9 years ago |
0 |
|
3 |
gpl-3.0 |
C++ |
| FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS |
| FPGA-Research-Manchester/fos |
40 |
|
0 |
0 |
over 5 years ago |
0 |
|
0 |
other |
VHDL |
| FOS - FPGA Operating System |
| Xilinx/ResNet50-PYNQ |
37 |
|
0 |
0 |
over 4 years ago |
2 |
April 15, 2020 |
1 |
bsd-3-clause |
C++ |
| Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ |
| maltanar/rosetta |
21 |
|
0 |
0 |
over 7 years ago |
0 |
|
0 |
bsd-2-clause |
Tcl |
| Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ |
