| dgschwend/zynqnet |
510 |
|
0 |
0 |
almost 9 years ago |
0 |
|
38 |
gpl-3.0 |
HTML |
| Master Thesis "ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural Network" |
| Xilinx/Vitis-AI-Tutorials |
305 |
|
0 |
0 |
over 2 years ago |
0 |
|
61 |
mit |
|
| ARM-software/SCALE-Sim |
294 |
|
0 |
0 |
almost 3 years ago |
0 |
|
0 |
mit |
Python |
| changwoolee/lenet5_hls |
188 |
|
0 |
0 |
over 4 years ago |
0 |
|
12 |
mit |
C++ |
| FPGA Accelerator for CNN using Vivado HLS |
| WalkerLau/Accelerating-CNN-with-FPGA |
164 |
|
0 |
0 |
over 6 years ago |
0 |
|
1 |
other |
C++ |
| This project accelerates CNN computation with the help of FPGA, for more than 50x speed-up compared with CPU. |
| TF2-Engine/TF2 |
74 |
|
0 |
0 |
almost 6 years ago |
0 |
|
12 |
apache-2.0 |
Python |
| An Open Source Deep Learning Inference Engine Based on FPGA |
| pp-Innovate/FPGA-ZynqNet |
56 |
|
0 |
0 |
almost 9 years ago |
0 |
|
3 |
gpl-3.0 |
C++ |
| FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS |
| taoyilee/clacc |
51 |
|
0 |
0 |
over 8 years ago |
0 |
|
0 |
mit |
Verilog |
| Deep Learning Accelerator (Convolution Neural Networks) |
| lirui-shanghaitech/CNN-Accelerator-VLSI |
48 |
|
0 |
0 |
about 3 years ago |
0 |
|
1 |
apache-2.0 |
Verilog |
| Convolutional accelerator kernel, target ASIC & FPGA |
| CNILeo/DNN-Accelerator |
45 |
|
0 |
0 |
almost 3 years ago |
0 |
|
0 |
mit |
VHDL |
| A DNN Accelerator implemented with RTL. |
