| chipsalliance/rocket-chip |
2,922 |
|
0 |
0 |
about 2 years ago |
9 |
May 14, 2020 |
269 |
other |
Scala |
| Rocket Chip Generator |
| darklife/darkriscv |
1,795 |
|
0 |
0 |
over 2 years ago |
0 |
|
9 |
bsd-3-clause |
Verilog |
| opensouce RISC-V cpu core implemented in Verilog from scratch in one night! |
| riscv-boom/riscv-boom |
1,524 |
|
0 |
0 |
about 2 years ago |
0 |
|
98 |
bsd-3-clause |
Scala |
| SonicBOOM: The Berkeley Out-of-Order Machine |
| ucb-bar/chipyard |
1,338 |
|
0 |
0 |
about 2 years ago |
0 |
|
170 |
bsd-3-clause |
C |
| An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more |
| openhwgroup/cv32e40p |
836 |
|
0 |
0 |
about 2 years ago |
0 |
|
52 |
other |
SystemVerilog |
| CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform |
| firesim/firesim |
778 |
|
0 |
0 |
about 2 years ago |
0 |
|
218 |
other |
Scala |
| FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility |
| chipsalliance/Cores-VeeR-EH1 |
746 |
|
0 |
0 |
almost 3 years ago |
0 |
|
14 |
apache-2.0 |
SystemVerilog |
| VeeR EH1 core |
| syntacore/scr1 |
688 |
|
0 |
0 |
over 2 years ago |
0 |
|
3 |
other |
SystemVerilog |
| SCR1 is a high-quality open-source RISC-V MCU core in Verilog |
| sergeykhbr/riscv_vhdl |
552 |
|
0 |
0 |
over 2 years ago |
0 |
|
2 |
apache-2.0 |
Verilog |
| Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators |
| ucb-bar/riscv-mini |
427 |
|
0 |
0 |
over 2 years ago |
0 |
|
3 |
other |
Scala |
| Simple RISC-V 3-stage Pipeline in Chisel |
