| SpinalHDL/VexRiscv |
2,135 |
|
0 |
0 |
over 2 years ago |
0 |
|
100 |
mit |
Assembly |
| A FPGA friendly 32 bit RISC-V CPU implementation |
| stnolting/neorv32 |
1,337 |
|
0 |
0 |
about 2 years ago |
0 |
|
15 |
bsd-3-clause |
VHDL |
| 🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. |
| sergeykhbr/riscv_vhdl |
552 |
|
0 |
0 |
over 2 years ago |
0 |
|
2 |
apache-2.0 |
Verilog |
| Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators |
| howerj/forth-cpu |
276 |
|
0 |
0 |
about 4 years ago |
0 |
|
0 |
|
VHDL |
| A Forth CPU and System on a Chip, based on the J1, written in VHDL |
| wfjm/w11 |
109 |
|
0 |
0 |
almost 3 years ago |
0 |
|
13 |
gpl-3.0 |
VHDL |
| PDP-11/70 CPU core and SoC |
| zylin/zpu |
104 |
|
0 |
0 |
almost 11 years ago |
0 |
|
0 |
|
VHDL |
| The Zylin ZPU |
| Domipheus/TPU |
82 |
|
0 |
0 |
over 9 years ago |
0 |
|
1 |
|
VHDL |
| TPU, The Test Processing Unit. Or Terrible Processing Unit. A simple 16-bit CPU in VHDL for education as to the dataflow within a CPU. Designed to run on miniSpartan6+. |
| SteffenReith/J1Sc |
72 |
|
0 |
0 |
over 3 years ago |
0 |
|
0 |
bsd-3-clause |
Scala |
| A reimplementation of a tiny stack CPU |
| Domipheus/RPU |
70 |
|
0 |
0 |
over 5 years ago |
0 |
|
0 |
apache-2.0 |
VHDL |
| Basic RISC-V CPU implementation in VHDL. |
| howerj/bit-serial |
65 |
|
0 |
0 |
over 2 years ago |
0 |
|
0 |
mit |
VHDL |
| A bit-serial CPU written in VHDL, with a simulator written in C. |
