| stnolting/neorv32 |
1,337 |
|
0 |
0 |
about 2 years ago |
0 |
|
15 |
bsd-3-clause |
VHDL |
| 🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. |
| jbush001/LispMicrocontroller |
85 |
|
0 |
0 |
about 2 years ago |
0 |
|
7 |
apache-2.0 |
Python |
| A microcontroller that natively executes a simple LISP dialect |
| MaJerle/stm32h7-dual-core-inter-cpu-async-communication |
66 |
|
0 |
0 |
over 2 years ago |
0 |
|
1 |
mit |
C |
| Inter-CPU asynchronous communication between Cortex-M7 and Cortex-M4 cores on STM32H7 dual core devices |
| deadsy/pycs |
49 |
|
0 |
0 |
about 3 years ago |
0 |
|
1 |
mit |
Python |
| Python Based ARM CoreSight Debug and Trace Tools |
| saursin/riscv-atom |
14 |
|
0 |
0 |
over 2 years ago |
0 |
|
2 |
mit |
C++ |
| An open-source 32-bit RISC-V soft-core processor for FPGAs. |
| osresearch/risc8 |
13 |
|
0 |
0 |
over 4 years ago |
0 |
|
1 |
|
Verilog |
| Mostly AVR compatible FPGA soft-core |
| ben-marshall/croyde-riscv |
10 |
|
0 |
0 |
about 4 years ago |
0 |
|
0 |
mit |
|
| A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions. |
| maxstrauch/kim-uno |
6 |
|
0 |
0 |
almost 7 years ago |
0 |
|
0 |
|
C |
| A portable, software defined dev kit for (retro) microprocessors. |
| TheLogicMaster/VHDLSonic |
6 |
|
0 |
0 |
over 3 years ago |
0 |
|
0 |
gpl-3.0 |
C++ |
| A custom 32-bit architecture, microcontroller, retro console, and software suite |
