| JulianKemmerer/PipelineC |
519 |
|
0 |
0 |
about 2 years ago |
0 |
|
82 |
gpl-3.0 |
Python |
| A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature. |
| gtaylormb/opl3_fpga |
225 |
|
0 |
0 |
over 6 years ago |
0 |
|
6 |
lgpl-3.0 |
VHDL |
| Reverse engineered SystemVerilog RTL version of the Yamaha OPL3 (YMF262) FM Synthesizer |
| kevinpt/vhdl-extras |
156 |
|
0 |
0 |
almost 3 years ago |
0 |
|
3 |
|
VHDL |
| Flexible VHDL library |
| kevinpt/symbolator |
73 |
|
2 |
0 |
over 5 years ago |
3 |
October 19, 2017 |
12 |
mit |
Python |
| HDL symbol generator |
| nullobject/sdram-fpga |
65 |
|
0 |
0 |
over 5 years ago |
0 |
|
3 |
mit |
VHDL |
| A FPGA core for a simple SDRAM controller. |
| preusser/q27 |
53 |
|
0 |
0 |
over 8 years ago |
0 |
|
1 |
agpl-3.0 |
VHDL |
| 27-Queens Puzzle: Massively Parellel Enumeration and Solution Counting |
| pedrorivera/SiaFpgaMiner |
44 |
|
0 |
0 |
about 8 years ago |
0 |
|
1 |
mit |
VHDL |
| VHDL FPGA design of an optimized Blake2b pipeline to mine Siacoin |
| hamsternz/Rudi-RV32I |
41 |
|
0 |
0 |
over 5 years ago |
0 |
|
2 |
mit |
VHDL |
| A rudimental RISCV CPU supporting RV32I instructions, in VHDL |
| freitz85/AppleIISd |
37 |
|
0 |
0 |
over 4 years ago |
0 |
|
2 |
|
VHDL |
| SD card based ProFile replacement for IIe |
| fcayci/vhdl-hdmi-out |
33 |
|
0 |
0 |
over 3 years ago |
0 |
|
1 |
mit |
VHDL |
| HDMI Out VHDL code for 7-series Xilinx FPGAs |
