| verilog-to-routing/vtr-verilog-to-routing |
925 |
|
0 |
0 |
about 2 years ago |
0 |
|
447 |
other |
C++ |
| Verilog to Routing -- Open Source CAD Flow for FPGA Research |
| olofk/edalize |
573 |
|
2 |
3 |
about 2 years ago |
24 |
December 08, 2023 |
91 |
bsd-2-clause |
Python |
| An abstraction library for interfacing EDA tools |
| JulianKemmerer/PipelineC |
519 |
|
0 |
0 |
about 2 years ago |
0 |
|
82 |
gpl-3.0 |
Python |
| A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature. |
| danielholanda/LeFlow |
329 |
|
0 |
0 |
over 6 years ago |
0 |
|
1 |
other |
Verilog |
| Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks |
| VLSI-EDA/PoC |
324 |
|
0 |
0 |
over 5 years ago |
0 |
|
31 |
other |
VHDL |
| IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany |
| f4pga/f4pga-arch-defs |
242 |
|
0 |
0 |
about 2 years ago |
0 |
|
366 |
isc |
Jupyter Notebook |
| FOSS architecture definitions of FPGA hardware useful for doing PnR device generation. |
| ferrandi/PandA-bambu |
192 |
|
0 |
0 |
over 2 years ago |
0 |
|
8 |
gpl-3.0 |
C++ |
| PandA-bambu public repository |
| masc-ucsc/livehd |
192 |
|
0 |
0 |
about 2 years ago |
4 |
June 06, 2018 |
11 |
other |
Verilog |
| Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation |
| dpretet/async_fifo |
173 |
|
0 |
0 |
about 3 years ago |
0 |
|
0 |
other |
Verilog |
| A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog |
| tymonx/logic |
121 |
|
0 |
0 |
over 6 years ago |
0 |
|
0 |
apache-2.0 |
SystemVerilog |
| CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs. |
