| hukenovs/dsp-theory |
792 |
|
0 |
0 |
about 3 years ago |
0 |
|
1 |
gpl-3.0 |
Jupyter Notebook |
| Theory of digital signal processing (DSP): signals, filtration (IIR, FIR, CIC, MAF), transforms (FFT, DFT, Hilbert, Z-transform) etc. |
| ZipCPU/dblclockfft |
195 |
|
0 |
0 |
about 2 years ago |
0 |
|
3 |
|
C++ |
| A configurable C++ generator of pipelined Verilog FFT cores |
| loykylewong/FPGA-Application-Development-and-Simulation |
96 |
|
0 |
0 |
over 2 years ago |
0 |
|
1 |
mit |
SystemVerilog |
| 《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS). |
| gasparka/spectrogram |
73 |
|
0 |
0 |
over 5 years ago |
13 |
October 21, 2020 |
2 |
|
Python |
| 80MHz bandwidth with LimeSDR-Mini and GQRX |
| hukenovs/intfftk |
56 |
|
0 |
0 |
about 3 years ago |
0 |
|
0 |
gpl-3.0 |
VHDL |
| Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0. |
| owocomm-0/fpga-fft |
42 |
|
0 |
0 |
about 5 years ago |
0 |
|
1 |
other |
VHDL |
| A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm |
| mattvenn/fpga-sdft |
32 |
|
0 |
0 |
almost 6 years ago |
0 |
|
1 |
|
Verilog |
| sliding DFT for FPGA, targetting Lattice ICE40 1k |
| hukenovs/fp23fftk |
31 |
|
0 |
0 |
almost 4 years ago |
0 |
|
0 |
gpl-3.0 |
VHDL |
| Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL). |
| MohammedRashad/FPGA-Speech-Recognition |
28 |
|
0 |
0 |
about 8 years ago |
0 |
|
0 |
gpl-3.0 |
VHDL |
| Expiremental Speech Recognition System using VHDL & MATLAB. |
| abdelazeem201/Design-and-ASIC-Implementation-of-32-Point-FFT-Processor |
20 |
|
0 |
0 |
over 2 years ago |
0 |
|
0 |
mit |
Verilog |
| I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be built using the proposed processing element. The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of adders required in the conventional pipelined FFT designs. In order to produce the output sequence in normal order, we also present a bit reverser, which can achieve a 50% reduction in memory usage. |
