| parallella/parallella-examples |
375 |
|
0 |
0 |
almost 7 years ago |
0 |
|
3 |
|
VHDL |
| Community created parallella projects |
| hukenovs/intfftk |
56 |
|
0 |
0 |
about 3 years ago |
0 |
|
0 |
gpl-3.0 |
VHDL |
| Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0. |
| strath-sdr/rfsoc_sam |
46 |
|
0 |
0 |
almost 3 years ago |
0 |
|
2 |
bsd-3-clause |
VHDL |
| RFSoC Spectrum Analyser Module on PYNQ. |
| owocomm-0/fpga-fft |
42 |
|
0 |
0 |
about 5 years ago |
0 |
|
1 |
other |
VHDL |
| A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm |
| hukenovs/fp23fftk |
31 |
|
0 |
0 |
almost 4 years ago |
0 |
|
0 |
gpl-3.0 |
VHDL |
| Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL). |
| MohammedRashad/FPGA-Speech-Recognition |
28 |
|
0 |
0 |
about 8 years ago |
0 |
|
0 |
gpl-3.0 |
VHDL |
| Expiremental Speech Recognition System using VHDL & MATLAB. |
| abdelazeem201/Design-and-ASIC-Implementation-of-32-Point-FFT-Processor |
20 |
|
0 |
0 |
over 2 years ago |
0 |
|
0 |
mit |
Verilog |
| I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be built using the proposed processing element. The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of adders required in the conventional pipelined FFT designs. In order to produce the output sequence in normal order, we also present a bit reverser, which can achieve a 50% reduction in memory usage. |
| thasti/fft |
16 |
|
0 |
0 |
almost 7 years ago |
0 |
|
0 |
other |
VHDL |
| synthesizable FFT IP block for FPGA designs |
| hukenovs/math |
15 |
|
0 |
0 |
over 5 years ago |
0 |
|
|
gpl-3.0 |
MATLAB |
| Useful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.) |
| delhatch/Spectrum |
12 |
|
0 |
0 |
about 8 years ago |
0 |
|
0 |
|
VHDL |
| Spectrum analyzer system using a 512-point FFT, in a Cyclone IV FPGA. Reads i2s audio from the codec and then does all FFT/VGA functions. Nios just reads the FFT result and draws the display bars. VGA frame buffer on-chip. VGA signals generated on-chip. See the included video files to watch it in action. |
