| open-sdr/openwifi-hw |
560 |
|
0 |
0 |
over 2 years ago |
0 |
|
5 |
agpl-3.0 |
Verilog |
| open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware |
| kangyuzhe666/ZYNQ7010-7020_AD9363 |
198 |
|
0 |
0 |
over 3 years ago |
0 |
|
3 |
apache-2.0 |
VHDL |
| 基于ZYNQ+AD9363的开源SDR硬件 |
| strath-sdr/rfsoc_qpsk |
62 |
|
0 |
0 |
almost 3 years ago |
0 |
|
0 |
bsd-3-clause |
VHDL |
| PYNQ example of using the RFSoC as a QPSK transceiver. |
| daveshah1/RFToolSDR |
49 |
|
0 |
0 |
over 8 years ago |
0 |
|
0 |
mit |
VHDL |
| AD9361 based USB3 SDR |
| strath-sdr/rfsoc_sam |
46 |
|
0 |
0 |
almost 3 years ago |
0 |
|
2 |
bsd-3-clause |
VHDL |
| RFSoC Spectrum Analyser Module on PYNQ. |
| srsran/zynq_timestamping |
36 |
|
0 |
0 |
over 3 years ago |
0 |
|
5 |
agpl-3.0 |
VHDL |
| Open source Zynq timestamping implementation from Software Radio Systems (SRS) |
| vankxr/icyradio |
15 |
|
0 |
0 |
over 2 years ago |
0 |
|
0 |
gpl-3.0 |
VHDL |
| Over-engineered SDR development board |
| strath-sdr/rfsoc_radio |
14 |
|
0 |
0 |
almost 3 years ago |
0 |
|
0 |
bsd-3-clause |
VHDL |
| PYNQ example of using the RFSoC as a QPSK/BPSK radio transceiver. |
| 0xee/NfcEmu |
8 |
|
0 |
0 |
over 11 years ago |
0 |
|
0 |
|
VHDL |
| SDR/FPGA-based NFC/RFID Emulator |
| natsfr/LimeSDR_DVBSGateware |
7 |
|
0 |
0 |
over 6 years ago |
0 |
|
1 |
apache-2.0 |
VHDL |
| Optimised gateware for lime sdr mini |
