| darklife/darkriscv |
1,795 |
|
0 |
0 |
over 2 years ago |
0 |
|
9 |
bsd-3-clause |
Verilog |
| opensouce RISC-V cpu core implemented in Verilog from scratch in one night! |
| steve-m/kalibrate-rtl |
379 |
|
0 |
0 |
about 4 years ago |
0 |
|
18 |
bsd-2-clause |
C++ |
| fork of http://thre.at/kalibrate/ for use with rtl-sdr devices |
| ZipCPU/autofpga |
153 |
|
0 |
0 |
about 2 years ago |
0 |
|
2 |
gpl-3.0 |
C++ |
| A utility for Composing FPGA designs from Peripherals |
| blackmesalabs/hyperram |
39 |
|
0 |
0 |
over 7 years ago |
0 |
|
0 |
|
Verilog |
| Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC |
| mattvenn/vga-clock |
33 |
|
0 |
0 |
over 4 years ago |
0 |
|
1 |
apache-2.0 |
Verilog |
| Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle. |
| olofk/fifo |
18 |
|
0 |
0 |
almost 6 years ago |
0 |
|
1 |
|
Verilog |
| Generic FIFO implementation with optional FWFT |
| lostpfg/SHA-256-HDL |
6 |
|
0 |
0 |
almost 9 years ago |
0 |
|
0 |
|
VHDL |
| An implementation of original SHA-256 hash function in (RTL) VHDL |
