| darklife/darkriscv |
1,795 |
|
0 |
0 |
over 2 years ago |
0 |
|
9 |
bsd-3-clause |
Verilog |
| opensouce RISC-V cpu core implemented in Verilog from scratch in one night! |
| sylefeb/Silice |
1,199 |
|
0 |
0 |
about 2 years ago |
0 |
|
73 |
other |
C++ |
| Silice is an open source language that simplifies prototyping and writing algorithms on FPGA architectures. |
| hdl-util/hdmi |
892 |
|
0 |
0 |
over 2 years ago |
0 |
|
8 |
other |
SystemVerilog |
| Send video/audio over HDMI on an FPGA |
| JulianKemmerer/PipelineC |
519 |
|
0 |
0 |
about 2 years ago |
0 |
|
82 |
gpl-3.0 |
Python |
| A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature. |
| myriadrf/LimeSDR-USB |
272 |
|
0 |
0 |
over 5 years ago |
0 |
|
4 |
|
ANTLR |
| USB 3.0 version of the LimeSDR board |
| jhshi/openofdm |
251 |
|
0 |
0 |
about 3 years ago |
0 |
|
8 |
apache-2.0 |
Verilog |
| Sythesizable, modular Verilog implementation of 802.11 OFDM decoder. |
| gtaylormb/opl3_fpga |
225 |
|
0 |
0 |
over 6 years ago |
0 |
|
6 |
lgpl-3.0 |
VHDL |
| Reverse engineered SystemVerilog RTL version of the Yamaha OPL3 (YMF262) FM Synthesizer |
| ZipCPU/dblclockfft |
195 |
|
0 |
0 |
about 2 years ago |
0 |
|
3 |
|
C++ |
| A configurable C++ generator of pipelined Verilog FFT cores |
| ZipCPU/autofpga |
153 |
|
0 |
0 |
about 2 years ago |
0 |
|
2 |
gpl-3.0 |
C++ |
| A utility for Composing FPGA designs from Peripherals |
| avakar/usbcorev |
146 |
|
0 |
0 |
over 3 years ago |
0 |
|
2 |
other |
Verilog |
| A full-speed device-side USB peripheral core written in Verilog. |
