| sylefeb/Silice |
1,199 |
|
0 |
0 |
about 2 years ago |
0 |
|
73 |
other |
C++ |
| Silice is an open source language that simplifies prototyping and writing algorithms on FPGA architectures. |
| alialaei110/HDLab-FPGA-Development-Board |
43 |
|
0 |
0 |
over 2 years ago |
0 |
|
0 |
mit |
VHDL |
| Open source FPGA development platform |
| adamwalker/clash-utils |
42 |
|
0 |
0 |
almost 3 years ago |
0 |
|
8 |
bsd-3-clause |
Haskell |
| A collection of reusable Clash designs/examples |
| brianwchh/grassrootsstartup-ComputerVsion-zynq |
35 |
|
0 |
0 |
almost 3 years ago |
0 |
|
0 |
other |
C |
| Gordonei/MyHDL-based-FPGA-DSP-Toolflow |
21 |
|
0 |
0 |
over 13 years ago |
0 |
|
0 |
|
Python |
| A library for generating Software Defined Radio-intended DSP code for FPGAs that makes use of the MyHDL (www.myhdl.org) Python library. Targeted at the Rhino Project (see URL). |
| nbrummel/SIFT-implementation-in-Verilog |
21 |
|
0 |
0 |
over 12 years ago |
0 |
|
0 |
|
|
| Using Verilog to implement the SIFT algorithm into an FPGA for small robotic situations |
| MorrisMA/Booth_Multipliers |
19 |
|
0 |
0 |
over 5 years ago |
0 |
|
0 |
|
Verilog |
| Parameterized Booth Multiplier in Verilog 2001 |
| JarrettR/FPGA-Cryptoparty |
18 |
|
0 |
0 |
over 8 years ago |
0 |
|
3 |
gpl-3.0 |
Java |
| A very very fast VHDL implementation of the WPA2 encryption algorithm. |
| williamyang4978/PipeCNN_Winograd |
17 |
|
0 |
0 |
almost 5 years ago |
0 |
|
5 |
other |
C++ |
| An OpenCL-Based FPGA Accelerator for Compressed YOLOv2 |
| dhm2013724/Xilinx_FPGA_HLS-Mapping-Neural-Network-to-Hardware |
14 |
|
0 |
0 |
over 7 years ago |
0 |
|
2 |
mit |
|
| At present, just an example to show how to map the detection algorithm YOLOv2 from model to FPGA |
