| jhshi/openofdm |
251 |
|
0 |
0 |
about 3 years ago |
0 |
|
8 |
apache-2.0 |
Verilog |
| Sythesizable, modular Verilog implementation of 802.11 OFDM decoder. |
| russdill/bch_verilog |
57 |
|
0 |
0 |
over 3 years ago |
0 |
|
4 |
other |
Verilog |
| Verilog based BCH encoder/decoder |
| WangXuan95/FPGA-PNG-decoder |
57 |
|
0 |
0 |
over 2 years ago |
0 |
|
0 |
gpl-3.0 |
Verilog |
| An FPGA-based PNG image decoder, which can extract original pixels from PNG files. 基于FPGA的PNG图象解码器，可以从PNG文件中解码出原始像素。 |
| nxbyte/Verilog-Projects |
49 |
|
0 |
0 |
over 6 years ago |
0 |
|
|
mit |
Verilog |
| This repository contains source code for past labs and projects involving FPGA and Verilog based designs |
| ultraembedded/core_jpeg |
31 |
|
0 |
0 |
over 5 years ago |
0 |
|
0 |
apache-2.0 |
Verilog |
| High throughput JPEG decoder in Verilog for FPGA |
| biren15/Design-and-Verification-of-LDPC-Decoder |
17 |
|
0 |
0 |
over 8 years ago |
0 |
|
0 |
|
Verilog |
| - Designed the LDPC decoder in the Matlab using the min-sum approach. - Designed quantized RTL in Verilog with the min-sum approach and parallel architecture. - Created modules for all variants of the variable node unit(VNU) and the check-node unit(CNU) based on the H matrix. Created script for module instantiation of VNU and CNU as per the H matrix. - Verified the functionality of the Verilog implementation by self-checking test-bench in Verilog to compare the results with Matlab. |
| jkelley/irig-decoder |
13 |
|
0 |
0 |
over 3 years ago |
0 |
|
0 |
mit |
Verilog |
| Firmware IRIG-B decoder |
| cea-wind/hls_ldpc_dec |
9 |
|
0 |
0 |
almost 7 years ago |
0 |
|
0 |
gpl-3.0 |
C++ |
| Full piplined LDPC decoder (IEEE 802.16e) implement in FPGA using Xilinx HLS(C synthesis to Verilog Codes).. |
| aekanman/FPGA-video-decoder |
8 |
|
0 |
0 |
about 8 years ago |
0 |
|
0 |
mit |
Verilog |
| :space_invader: Design and implementation of a video decoder on an Altera Cyclone V FPGA board. |
| jfoshea/Viterbi-Decoder-in-Verilog |
6 |
|
0 |
0 |
almost 8 years ago |
0 |
|
0 |
|
Verilog |
| An efficient implementation of the Viterbi decoding algorithm in Verilog |
