| darklife/darkriscv |
1,795 |
|
0 |
0 |
over 2 years ago |
0 |
|
9 |
bsd-3-clause |
Verilog |
| opensouce RISC-V cpu core implemented in Verilog from scratch in one night! |
| google/xls |
1,087 |
|
0 |
0 |
about 2 years ago |
0 |
|
607 |
apache-2.0 |
C++ |
| XLS: Accelerated HW Synthesis |
| WangXuan95/Verilog-FixedPoint |
75 |
|
0 |
0 |
over 2 years ago |
0 |
|
0 |
gpl-3.0 |
Verilog |
| A Verilog fixed-point lib: custom bit width, arithmetic, converting to float, with single cycle & pipeline version. 一个Verilog定点数库，提供算术运算、与浮点数的互相转换，包含单周期和流水线两种实现。 |
| russdill/bch_verilog |
57 |
|
0 |
0 |
over 3 years ago |
0 |
|
4 |
other |
Verilog |
| Verilog based BCH encoder/decoder |
| mhyousefi/MIPS-pipeline-processor |
52 |
|
0 |
0 |
over 6 years ago |
0 |
|
1 |
|
Verilog |
| A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding |
| google/autopiper |
40 |
|
0 |
0 |
over 10 years ago |
0 |
|
0 |
apache-2.0 |
C++ |
| Evensgn/RISC-V-CPU |
34 |
|
0 |
0 |
over 8 years ago |
0 |
|
1 |
|
Verilog |
| RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL. |
| lmxyy/Computer-Architecture-Task-2 |
25 |
|
0 |
0 |
about 8 years ago |
0 |
|
0 |
mit |
Verilog |
| Riscv32 CPU Project |
| FAST-Switch/fast |
22 |
|
0 |
0 |
over 9 years ago |
0 |
|
0 |
apache-2.0 |
Verilog |
| FAST |
| fallen/tinycpu |
21 |
|
0 |
0 |
about 14 years ago |
0 |
|
0 |
|
Verilog |
| Tiny CPU is a small 32-bit CPU done mostly as a hobby for educational purposes. |
