| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| aquaxis/synverll | 12 | 0 | 0 | almost 10 years ago | 0 | 0 | mit | C | ||
| RainEggplant/vscode-verilog-integration | 10 | 0 | 0 | over 5 years ago | 0 | 0 | ||||
| 使用 VSCode 舒适地开发 Verilog | ||||||||||
| GregMefford/vlsi681spring09 | 8 | 0 | 0 | almost 17 years ago | 0 | 0 | Verilog | |||
| Class Project for 681 VLSI System Design Course at The University of Cincinnati, Spring 2009 | ||||||||||
| Ncerzzk/MyBlog | 6 | 0 | 0 | almost 4 years ago | 0 | 162 | Ruby | |||
| Git简易博客 | ||||||||||
| robbertkrebbers/corn | 5 | 0 | 0 | about 14 years ago | 0 | 1 | gpl-2.0 | Verilog | ||
| cambridgehackers/atomicc | 5 | 0 | 0 | about 3 years ago | 0 | 0 | gpl-2.0 | Shell | ||
| Generate Verilog from Atomicc IR files (which are generated from llvm-translate) | ||||||||||
