| triSYCL/triSYCL |
424 |
|
0 |
0 |
over 2 years ago |
0 |
|
116 |
other |
C++ |
| Generic system-wide modern C++ for heterogeneous platforms with SYCL from Khronos Group |
| hanchenye/scalehls |
157 |
|
0 |
0 |
over 2 years ago |
0 |
|
26 |
other |
MLIR |
| A scalable High-Level Synthesis framework on MLIR |
| KASIRGA-KIZIL/tekno-kizil |
129 |
|
0 |
0 |
over 2 years ago |
0 |
|
3 |
gpl-3.0 |
Verilog |
| KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi |
| libmir/dcompute |
116 |
|
0 |
0 |
about 4 years ago |
2 |
October 15, 2017 |
18 |
bsl-1.0 |
D |
| DCompute: Native execution of D on GPUs and other Accelerators |
| triSYCL/sycl |
98 |
|
0 |
0 |
over 2 years ago |
0 |
|
54 |
other |
|
| SYCL for Vitis: Experimental fusion of triSYCL with Intel SYCL oneAPI DPC++ up-streaming effort into Clang/LLVM |
| UCLA-VAST/AutoSA |
80 |
|
0 |
0 |
over 4 years ago |
0 |
|
3 |
mit |
C++ |
| AutoSA: Polyhedral-Based Systolic Array Compiler |
| nlsynth/iroha |
30 |
|
0 |
0 |
almost 5 years ago |
0 |
|
0 |
bsd-3-clause |
C++ |
| Intermediate Representation Of Hardware Abstraction (LLVM-ish for HLS) |
| Nic30/hwtHls |
20 |
|
0 |
0 |
almost 3 years ago |
0 |
|
0 |
mit |
Python |
| LLVM based HLS library for HWToolkit (hardware devel. toolkit) |
| zainryan/INSIDER-System |
17 |
|
0 |
0 |
over 5 years ago |
0 |
|
0 |
mit |
Verilog |
| An FPGA-based full-stack in-storage computing system. |
| cornell-zhang/datuner |
10 |
|
0 |
0 |
over 7 years ago |
0 |
|
9 |
bsd-3-clause |
LLVM |
| DATuner Repository |
