| intel/systemc-compiler |
205 |
|
0 |
0 |
about 2 years ago |
0 |
|
8 |
other |
C++ |
| This tool translates synthesizable SystemC code to synthesizable SystemVerilog. |
| hanchenye/scalehls |
157 |
|
0 |
0 |
over 2 years ago |
0 |
|
26 |
other |
MLIR |
| A scalable High-Level Synthesis framework on MLIR |
| zslwyuan/LLVM-9.0-Learner-Tutorial |
82 |
|
0 |
0 |
almost 4 years ago |
0 |
|
0 |
gpl-3.0 |
C++ |
| A blog for LLVM(v9.0.0 or v11.0.0) beginner, step by step, with detailed documents and comments. Record the way I learn LLVM and accomplish a complete project for FPGA High-Level Synthesis with it. |
| UCLA-VAST/AutoSA |
80 |
|
0 |
0 |
over 4 years ago |
0 |
|
3 |
mit |
C++ |
| AutoSA: Polyhedral-Based Systolic Array Compiler |
| nlsynth/iroha |
30 |
|
0 |
0 |
almost 5 years ago |
0 |
|
0 |
bsd-3-clause |
C++ |
| Intermediate Representation Of Hardware Abstraction (LLVM-ish for HLS) |
| Nic30/hwtHls |
20 |
|
0 |
0 |
almost 3 years ago |
0 |
|
0 |
mit |
Python |
| LLVM based HLS library for HWToolkit (hardware devel. toolkit) |
| zjru/COMBA |
19 |
|
0 |
0 |
over 5 years ago |
0 |
|
1 |
gpl-3.0 |
C++ |
| A Comprehensive Model-Based Analysis Framework for High Level Synthesis of Real Applications |
| sabbaghm/c-ll-verilog |
10 |
|
0 |
0 |
about 9 years ago |
0 |
|
0 |
mit |
C++ |
| An LLVM based mini-C to Verilog High-level Synthesis tool |
