| YosysHQ/yosys |
2,998 |
|
0 |
0 |
about 2 years ago |
0 |
|
435 |
isc |
C++ |
| Yosys Open SYnthesis Suite |
| nvdla/hw |
1,254 |
|
0 |
0 |
about 4 years ago |
0 |
|
193 |
other |
Verilog |
| RTL, Cmodel, and testbench for NVDLA |
| google/xls |
1,087 |
|
0 |
0 |
about 2 years ago |
0 |
|
607 |
apache-2.0 |
C++ |
| XLS: Accelerated HW Synthesis |
| verilog-to-routing/vtr-verilog-to-routing |
925 |
|
0 |
0 |
about 2 years ago |
0 |
|
447 |
other |
C++ |
| Verilog to Routing -- Open Source CAD Flow for FPGA Research |
| drom/awesome-hdl |
830 |
|
0 |
0 |
about 2 years ago |
0 |
|
1 |
|
|
| Hardware Description Languages |
| itsFrank/MinecraftHDL |
595 |
|
0 |
0 |
over 5 years ago |
0 |
|
7 |
|
SystemVerilog |
| A Verilog synthesis flow for Minecraft redstone circuits |
| olofk/edalize |
573 |
|
2 |
3 |
about 2 years ago |
24 |
December 08, 2023 |
91 |
bsd-2-clause |
Python |
| An abstraction library for interfacing EDA tools |
| danielholanda/LeFlow |
329 |
|
0 |
0 |
over 6 years ago |
0 |
|
1 |
other |
Verilog |
| Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks |
| NNgen/nngen |
281 |
|
0 |
0 |
over 2 years ago |
5 |
September 12, 2023 |
31 |
apache-2.0 |
Python |
| NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network |
| PyHDI/veriloggen |
275 |
|
1 |
0 |
over 2 years ago |
75 |
September 12, 2023 |
19 |
apache-2.0 |
Python |
| Veriloggen: A Mixed-Paradigm Hardware Construction Framework |
