| drom/awesome-hdl |
830 |
|
0 |
0 |
about 2 years ago |
0 |
|
1 |
|
|
| Hardware Description Languages |
| ben-marshall/awesome-open-hardware-verification |
353 |
|
0 |
0 |
over 2 years ago |
0 |
|
1 |
mit |
|
| A List of Free and Open Source Hardware Verification Tools and Frameworks |
| troyguo/awesome-dv |
76 |
|
0 |
0 |
about 4 years ago |
0 |
|
0 |
|
|
| Awesome ASIC design verification |
| abdelazeem201/ASIC-Design-Roadmap |
49 |
|
0 |
0 |
almost 3 years ago |
0 |
|
0 |
mit |
Verilog |
| The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product is typically quite small (measured in nanometers), this long journey is interesting and filled with many engineering challenges. |
| mikeroyal/Verilog-SystemVerilog-Guide |
41 |
|
0 |
0 |
over 2 years ago |
0 |
|
0 |
|
SystemVerilog |
| Verilog/SystemVerilog Guide |
| fukatani/awesome-hdl |
14 |
|
0 |
0 |
over 9 years ago |
0 |
|
1 |
other |
|
| A curated list of awesome HDL, libraries, typical implementation and references. |
