| mit-plv/koika |
84 |
|
0 |
0 |
about 4 years ago |
0 |
|
7 |
gpl-3.0 |
Coq |
| A core language for rule-based hardware design 🦑 |
| andrejbauer/Homotopy |
76 |
|
0 |
0 |
about 15 years ago |
0 |
|
1 |
|
Verilog |
| Homotopy theory in Coq. |
| ymherklotz/vericert |
73 |
|
0 |
0 |
about 2 years ago |
0 |
|
4 |
gpl-3.0 |
Coq |
| A formally verified high-level synthesis tool based on CompCert and written in Coq. |
| lulinchen/cnn_open |
60 |
|
0 |
0 |
over 7 years ago |
0 |
|
0 |
|
Coq |
| A hardware implementation of CNN, written by Verilog and synthesized on FPGA |
| PrimeMHD/FPGA_ThreeLevelStorage |
23 |
|
0 |
0 |
almost 6 years ago |
0 |
|
0 |
gpl-3.0 |
Coq |
| 【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。 |
| dpretet/friscv |
12 |
|
0 |
0 |
over 2 years ago |
0 |
|
1 |
mit |
Coq |
| RISCV CPU implementation in SystemVerilog |
| KevinHexin/FPGA-Bicubic-interpolation |
10 |
|
0 |
0 |
over 6 years ago |
0 |
|
0 |
gpl-3.0 |
Coq |
| use Verilog HDL implemente bicubic interpolation in FPGA |
| robbertkrebbers/corn |
5 |
|
0 |
0 |
about 14 years ago |
0 |
|
1 |
gpl-2.0 |
Verilog |
| tomprince/rippling |
5 |
|
0 |
0 |
over 14 years ago |
0 |
|
0 |
lgpl-2.1 |
Verilog |
| Sean Wilson's rippling plugin. |
