| hunterlew/convolution_network_on_FPGA |
187 |
|
0 |
0 |
about 8 years ago |
0 |
|
15 |
|
Verilog |
| CNN acceleration on virtex-7 FPGA with verilog HDL |
| QShen3/CNN-FPGA |
109 |
|
0 |
0 |
almost 8 years ago |
0 |
|
3 |
mit |
Verilog |
| 使用Verilog实现的CNN模块，可以方便的在FPGA项目中使用 |
| ilaydayaman/CNN_for_SLR |
79 |
|
0 |
0 |
over 2 years ago |
0 |
|
0 |
bsd-2-clause |
Verilog |
| A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA. |
| dem123456789/FPGA-CNN |
76 |
|
0 |
0 |
about 8 years ago |
0 |
|
0 |
mit |
Verilog |
| FPGA implementation of Cellular Neural Network (CNN) |
| lulinchen/cnn_open |
60 |
|
0 |
0 |
over 7 years ago |
0 |
|
0 |
|
Coq |
| A hardware implementation of CNN, written by Verilog and synthesized on FPGA |
| taoyilee/clacc |
51 |
|
0 |
0 |
over 8 years ago |
0 |
|
0 |
mit |
Verilog |
| Deep Learning Accelerator (Convolution Neural Networks) |
| lirui-shanghaitech/CNN-Accelerator-VLSI |
48 |
|
0 |
0 |
about 3 years ago |
0 |
|
1 |
apache-2.0 |
Verilog |
| Convolutional accelerator kernel, target ASIC & FPGA |
| chenhaoc/cnnhwpe |
46 |
|
0 |
0 |
almost 4 years ago |
0 |
|
2 |
|
Verilog |
| AniketBadhan/Convolutional-Neural-Network |
37 |
|
0 |
0 |
over 8 years ago |
0 |
|
4 |
|
Verilog |
| Implementation of CNN using Verilog |
| abarajithan11/deepsocflow |
28 |
|
0 |
0 |
over 2 years ago |
0 |
|
0 |
apache-2.0 |
Python |
| An Open Workflow to Build Custom SoCs and run Deep Models at the Edge |
