| lnis-uofu/OpenFPGA |
692 |
|
0 |
0 |
about 2 years ago |
0 |
|
103 |
mit |
Verilog |
| An Open-source FPGA IP Generator |
| sheldonucr/ucr-eecs168-lab |
423 |
|
0 |
0 |
about 3 years ago |
0 |
|
70 |
|
Verilog |
| The lab schedules for EECS168 at UC Riverside |
| Vitorian/awesome-fpga |
150 |
|
0 |
0 |
almost 9 years ago |
0 |
|
0 |
gpl-3.0 |
|
| A collection of resources on FPGA devices and development in general |
| cornell-brg/pymtl |
149 |
|
0 |
0 |
over 6 years ago |
0 |
|
81 |
bsd-3-clause |
Python |
| Python-based hardware modeling framework |
| cambridgehackers/fpgamake |
78 |
|
0 |
0 |
almost 4 years ago |
0 |
|
2 |
|
Tcl |
| Generates Makefiles to synthesize, place, and route verilog using Vivado |
| loongson-education/nscscc-wiki |
60 |
|
0 |
0 |
about 5 years ago |
0 |
|
0 |
|
|
| NSCSCC 信息整合 |
| embecosm/chiphack |
43 |
|
0 |
0 |
almost 8 years ago |
0 |
|
2 |
other |
Verilog |
| Repository and Wiki for Chip Hack events. |
| DidierMalenfant/openFPGA-tutorials |
26 |
|
0 |
0 |
over 2 years ago |
0 |
|
0 |
mit |
|
| A collection of tutorials and resources for the openFPGA platform. |
| peepo/verilog_tutorials_BB |
16 |
|
0 |
0 |
about 10 years ago |
0 |
|
0 |
|
Verilog |
| verilog tutorials for iCE40HX8K Breakout Board |
| ZipCPU/website |
13 |
|
0 |
0 |
about 2 years ago |
0 |
|
0 |
|
HTML |
| The ZipCPU blog |
