| ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA |
231 |
|
0 |
0 |
over 3 years ago |
0 |
|
15 |
apache-2.0 |
Verilog |
| Verilog Generator of Neural Net Digit Detector for FPGA |
| taoyilee/clacc |
51 |
|
0 |
0 |
over 8 years ago |
0 |
|
0 |
mit |
Verilog |
| Deep Learning Accelerator (Convolution Neural Networks) |
| SymbioticEDA/MARLANN |
46 |
|
0 |
0 |
almost 7 years ago |
0 |
|
0 |
|
Verilog |
| Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks |
| HWAC-DL/hwac_object_tracker |
24 |
|
0 |
0 |
over 7 years ago |
0 |
|
0 |
|
HTML |
| FPGA accelerated TinyYOLO v2 object detection neural network |
| romulus0914/CNN_VGG19_verilog |
20 |
|
0 |
0 |
over 8 years ago |
0 |
|
2 |
|
Verilog |
| Convolution Neural Network of vgg19 model in verilog |
| ChFrenkel/ODIN |
17 |
|
0 |
0 |
almost 7 years ago |
0 |
|
2 |
other |
Verilog |
| ODIN online-learning digital spiking neural network (SNN) processor - HDL source code and documentation. |
| g0kul/vcnn |
16 |
|
0 |
0 |
about 8 years ago |
0 |
|
1 |
mit |
VHDL |
| Verilog Convolutional Neural Network on PYNQ |
| andywag/NeuralHDL |
13 |
|
0 |
0 |
over 8 years ago |
0 |
|
0 |
|
Verilog |
| EEESlab/combinational-bnn |
9 |
|
0 |
0 |
almost 8 years ago |
0 |
|
1 |
|
SystemVerilog |
| System Verilog code describing a fully combinational binarized neural network. |
| Merterm/BRAIN-M |
6 |
|
0 |
0 |
over 8 years ago |
0 |
|
2 |
|
Verilog |
| Brilliantly Radical Artificially Intelligent Neural Machine |
