| maikmerten/spu32 |
48 |
|
0 |
0 |
almost 4 years ago |
0 |
|
0 |
mit |
C |
| Small Processing Unit 32: A compact RV32I CPU written in Verilog |
| fpgaminer/fpgaminer-vanitygen |
17 |
|
0 |
0 |
about 13 years ago |
0 |
|
0 |
gpl-3.0 |
Verilog |
| Open Source Bitcoin Vanity Address Generation on FPGAs |
| cr88192/bgbtech_btsr1arch |
17 |
|
0 |
0 |
about 2 years ago |
0 |
|
0 |
mit |
C |
| BtSR1 and BJX2 ISA / CPU Architecture |
| dan-rodrigues/ics-adpcm |
16 |
|
0 |
0 |
over 5 years ago |
0 |
|
0 |
mit |
Verilog |
| Programmable multichannel ADPCM decoder for FPGA |
| jotego/jtcontra |
15 |
|
0 |
0 |
about 3 years ago |
0 |
|
0 |
gpl-3.0 |
Verilog |
| FPGA conversion of KONAMI's K007121-based games: Contra, Combat School, Labyrinth Runner, Fast Lane, MX5000 |
| gmish27/CPUonFPGA |
8 |
|
0 |
0 |
about 9 years ago |
0 |
|
0 |
|
Verilog |
| It's a basic computer designed using VERILOG on XILINX FPGA architecture. |
