| alexforencich/verilog-axi |
1,113 |
|
0 |
0 |
over 2 years ago |
0 |
|
40 |
mit |
Verilog |
| Verilog AXI components for FPGA implementation |
| stffrdhrn/sdram-controller |
131 |
|
0 |
0 |
almost 9 years ago |
0 |
|
1 |
|
Verilog |
| Verilog SDRAM memory controller |
| maikmerten/spu32 |
48 |
|
0 |
0 |
almost 4 years ago |
0 |
|
0 |
mit |
C |
| Small Processing Unit 32: A compact RV32I CPU written in Verilog |
| cjhonlyone/NandFlashController |
42 |
|
0 |
0 |
almost 4 years ago |
0 |
|
2 |
gpl-3.0 |
Verilog |
| AXI Interface Nand Flash Controller (Sync mode) |
| fpgaminer/fpgaminer-vanitygen |
17 |
|
0 |
0 |
about 13 years ago |
0 |
|
0 |
gpl-3.0 |
Verilog |
| Open Source Bitcoin Vanity Address Generation on FPGAs |
| cr88192/bgbtech_btsr1arch |
17 |
|
0 |
0 |
about 2 years ago |
0 |
|
0 |
mit |
C |
| BtSR1 and BJX2 ISA / CPU Architecture |
| dan-rodrigues/ics-adpcm |
16 |
|
0 |
0 |
over 5 years ago |
0 |
|
0 |
mit |
Verilog |
| Programmable multichannel ADPCM decoder for FPGA |
| jotego/jtcontra |
15 |
|
0 |
0 |
about 3 years ago |
0 |
|
0 |
gpl-3.0 |
Verilog |
| FPGA conversion of KONAMI's K007121-based games: Contra, Combat School, Labyrinth Runner, Fast Lane, MX5000 |
| gmish27/CPUonFPGA |
8 |
|
0 |
0 |
about 9 years ago |
0 |
|
0 |
|
Verilog |
| It's a basic computer designed using VERILOG on XILINX FPGA architecture. |
| skristiansson/diila |
7 |
|
0 |
0 |
over 10 years ago |
0 |
|
0 |
|
Verilog |
| A Device Independent Integrated Logic Analyzer |
